Historically, the emphasis on Single Event Upset (SEU) research has been devoted exclusively to memory circuits. Memory circuits perform vital functions in any digital system, as program stores, temporary registers and as elements of state machines which control digital circuits. An SEU, or soft error, caused by a charged particle striking a diffusion region in a memory element can prove catastrophic to an electro-mechanical system which relies upon that memory element for communication or control.
Great effort has been made to find memory structures which are immune to SEUs, or at least mitigate the effects of an upsetting event. The design of SEU immune memories, whether RAM or Flip-Flops, has tended to ignore system level problems, such as an SEU of a combinational logic gate which is sampled by a memory circuit, or an upset of a control signal such as a clock line or mux select.
It has been shown that transients propagated out or into memory elements from logic circuits is indeed a real problem. Research, to find general logic gate structures which are SEU immune, has been primarily limited to resistive or capacitive hardening, which are basically low pass filtering approaches. A logic/circuit design approach has been presented by S. Kang and D. Chu in "CMOS Circuit Design for Prevention of Single Event Upset", Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, 1986. The CMOS inverter buffers presented by Kang and Chu however, are susceptible to particle hits on the p-type diffusion. The pre-charged output node is susceptible to a particle strike on the n-type diffusion if the pulldown chain does not evaluate low.
It is an object of the present invention to provide a logic family which will be immune to single event upsets. It is a second object of the present invention to maintain a source of uncorrupted data, which can be used to restore the lost data to its original value after an SEU.